Each timer then takes 80MHz APB clock and divides it down via the prescaler to a frequency of their own liking. How much the 80MHz clock is divided down by is determined by the value set in the prescaler (i.e. the Divider). The divider can take be any 16-bit value.

November 29, 2020 - timer_config_t config = { .alarm_en = TIMER_ALARM_DIS, .counter_en = TIMER_AUTORELOAD_DIS, .intr_type = TIMER_INTR_LEVEL, .counter_dir = TIMER_COUNT_UP, .auto_reload = TIMER_AUTORELOAD_DIS, .divider = 2 // 1 / 250 ns per tick }; A few weeks ago I asked a similar question but it was only about changing clock frequency and not timer frequency. ... How to delete and restart hw timer (for interrupts) on demand for esp32 arduino (stepper motor controller application)

Im using the ESP32-Wrover-Kit with the Adafruit screen library and a ADS1220 ADC, the library to this one was made by Protocentral. Connecting the ADS in the same SPI port than the screen and using another pin on CS this works well (because I will need the other pins for other parts of the project). The ADC clock can go up 8MHz (and still works) and if I leave the frequency set of the function Adafruit_ILI9341.begin() empty it can go up to 40MHz.

March 10, 2019 - I want to use 80 MHz clock for my timer. But esp32 only allows us to use timer_divider values between 2 and 65536?

Divider: Sets how quickly the timer’s counter is “ticking”. The setting divider is used as a divisor of the incoming 80 MHz APB_CLK clock.

April 30, 2020 - the code in RF24.cpp for setting ... of SPI.h (or esp32-hal-spi.h for the ESP32) has clock dividers meant to be compatible with the 16Mhz arduino boards....

What would the best way to implement a clock divider with a GPIO as the clock source with ESP32-S3. For example, 160KHz clock is provided to GPIO3, and I want to generate 10 KHz (divided by 16) on GPIO4. I tried to figure out by going through the document but it was not obvious.

By default the clock source is APB_CLK (typically 80 MHz). Divider: Sets how quickly the timer’s counter is “ticking”. The setting divider is used as a divisor of the clock source.

Set hardware timer source clock divider.

February 17, 2025 - This clock is then scaled down ... of the prescaler in order to control the timer tick time. The 16-Bit prescaler can divide the APB_CLK by a factor from 2 to 65536....

We can put 0 to 3 values to use any which we need. The second value is “prescaler”, i.e. divider value to the clock frequency i.e. 80MHz. We have a 16bit prescaler so we can set any value from 2 to 65536.

September 25, 2020 - This RC oscillator generates a about 8.5 MHz clock signal output as the RC_FAST_CLK. The about 8.5 MHz signal output is also passed into a configurable divider, which by default divides the input clock frequency by 256, to generate a RC_FAST_D256_CLK.

Divider: How quickly the timer’s counter is “ticking”. This depends on the setting of divider, that will be used as divisor of the incoming 80 MHz APB_CLK clock.

Set hardware timer source clock divider.

September 23, 2020 - 579545Mhz frequency using the crystal 3. 3V Memory 4Mb Flash Clock Frequency 160Mhz Interface USB to Mac or PC WiFi 2. 0v will just read as 4095 . Ttgo T call V1. The strange thing is that 156. clock_div is an 8 bit divider 0 255 and each pulse can be defined by multiplying the resolution by ...

The selected clock source drives ... power mode and needs faster CPU accessing, the application can choose the · external high-speed crystal clock divided by 4 or the internal 8 MHz oscillator....

This RC oscillator generates a about 8.5 MHz clock signal output as the RC_FAST_CLK. The about 8.5 MHz signal output is also passed into a configurable divider, which by default divides the input clock frequency by 256, to generate a RC_FAST_D256_CLK.

ESP32-S3's root clocks are listed ... 17.5 MHz signal output is also passed into a configurable divider, which by default divides the input clock frequency by 256, to generate a RC_FAST_D256_CLK....

ESP32’s root clocks are listed in soc_root_clk_t: ... This RC oscillator generates a ~8.5MHz clock signal output as the RC_FAST_CLK. The ~8.5MHz signal output is also passed into a configurable divider, which by default divides the input clock frequency by 256, to generate a RC_FAST_D256_CLK.