1 week ago - Buffer resources may be passed to AMDGPU buffer intrinsics, and they may be converted to and from ``i128. Casting a buffer resource to a buffer fat pointer is permitted and adds an offset of 0. Buffer resources can be created from 64-bit pointers (which should be either generic or global) using the llvm.amdgcn.make.buffer.rsrc intrinsic, which takes the pointer, which becomes the base of the resource, the 16-bit stride (and swzizzle control) field stored in bits 63:48 of a V#, the 32-bit NumRecords/extent field (bits 95:64), and the 32-bit flags field (bits 127:96).

The memory model supported is based on the HSA memory model [HSA] which is based in turn on HRF-indirect with scope inclusion [HRF]. The happens-before relation is transitive over the synchronizes-with relation independent of scope and synchronizes-with allows the memory scope instances to be inclusive (see table AMDHSA LLVM Sync Scopes). This is different to the OpenCL [OpenCL] memory model which does not have scope inclusion and requires the memory scopes to exactly match. However, this is conservatively correct for OpenCL. The AMDGPU backend implements the following LLVM IR intrinsics.

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. - llvm-project/llvm/lib/Target/AMDGPU/AMDGPU.td at main · llvm/llvm-project

In general terms, operations or types should be added to this dialect when they wrap some AMD-specific functionality in a way that makes it work better with the MLIR ecosystem and its types or when those buitins would be needlessly complex to work with (such as if they features magic constants at the LLVM level). An additional set of operations that belong in this dialect are those that have chipset-specific differences that can be abstracted over in a useful way. ... amdgpu.mfma and amdgpu.wmma exist in order to make a large set of intrinsics more compatible with the MLIR type system (such as by allowing 8-bit float vectors to be passed as vector<N x f8E4M3FN> or vector<N x f8E4M2> instead of as packed 32-bit integers whose element type is controlled by separate operator-level constants.

A late change to the AMDGPU LLVM compiler back-end that may help efforts particularly for the ROCm compute support on RDNA3 hardware is finally merging support for using true 16-bit instructions and registers on all RDNA3 GPUs. Merged earlier this summer was [AMDGPU][True16] set true16 mode as default on gfx110x.

2. Conversion. The input value is converted to the expected type as described in the table below. Depending on operand kind, this conversion is performed by either assembler or AMDGPU H/W (or both).

The AMDGPU backend supports the following memory models: ... The HSA memory model uses a single happens-before relation for all address spaces (see Address Spaces). ... The OpenCL memory model which has separate happens-before relations for the global and local address spaces. Only a fence specifying both global and local address space, and seq_cst instructions join the relationships. Since the LLVM memfence instruction does not allow an address space to be specified the OpenCL fence has to conservatively assume both local and global address space was specified.

The AMDGPU backend supports the following memory models: ... The HSA memory model uses a single happens-before relation for all address spaces (see Address Spaces). ... The OpenCL memory model which has separate happens-before relations for the global and local address spaces. Only a fence specifying both global and local address space, and seq_cst instructions join the relationships. Since the LLVM memfence instruction does not allow an address space to be specified the OpenCL fence has to convervatively assume both local and global address space was specified.

The AMDGPU backend supports the following memory models: ... The HSA memory model uses a single happens-before relation for all address spaces (see Address Spaces). ... The OpenCL memory model which has separate happens-before relations for the global and local address spaces. Only a fence specifying both global and local address space, and seq_cst instructions join the relationships. Since the LLVM memfence instruction does not allow an address space to be specified the OpenCL fence has to convervatively assume both local and global address space was specified.

The AMDGPU backend supports the following memory models: ... The HSA memory model uses a single happens-before relation for all address spaces (see Address Spaces). ... The OpenCL memory model which has separate happens-before relations for the global and local address spaces. Only a fence specifying both global and local address space, and seq_cst instructions join the relationships. Since the LLVM memfence instruction does not allow an address space to be specified the OpenCL fence has to convervatively assume both local and global address space was specified.

July 9, 2021 - The memory model supported is based on the HSA memory model [HSA] which is based in turn on HRF-indirect with scope inclusion [HRF]. The happens-before relation is transitive over the synchronizes-with relation independent of scope and synchronizes-with allows the memory scope instances to be inclusive (see table AMDHSA LLVM Sync Scopes). This is different to the OpenCL [OpenCL] memory model which does not have scope inclusion and requires the memory scopes to exactly match. However, this is conservatively correct for OpenCL. The AMDGPU backend implements the following LLVM IR intrinsics.

The AMDGPU backend supports the following memory models: ... The HSA memory model uses a single happens-before relation for all address spaces (see Address Spaces). ... The OpenCL memory model which has separate happens-before relations for the global and local address spaces. Only a fence specifying both global and local address space, and seq_cst instructions join the relationships. Since the LLVM memfence instruction does not allow an address space to be specified the OpenCL fence has to convervatively assume both local and global address space was specified.

The memory model supported is based on the HSA memory model [HSA] which is based in turn on HRF-indirect with scope inclusion [HRF]. The happens-before relation is transitive over the synchronizes-with relation independent of scope and synchronizes-with allows the memory scope instances to be inclusive (see table AMDHSA LLVM Sync Scopes). This is different to the OpenCL [OpenCL] memory model which does not have scope inclusion and requires the memory scopes to exactly match. However, this is conservatively correct for OpenCL. The AMDGPU backend implements the following LLVM IR intrinsics.

The AMDGPU memory model supports both the HSA [HSA] memory model, and the OpenCL [OpenCL] memory model. The HSA memory model uses a single happens-before relation for all address spaces (see Address Spaces). The OpenCL memory model which has separate happens-before relations for the global and local address spaces, and only a fence specifying both global and local address space joins the relationships. Since the LLVM memfence instruction does not allow an address space to be specified the OpenCL fence has to convervatively assume both local and global address space was specified.

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The memory model supported is based on the HSA memory model [HSA] which is based in turn on HRF-indirect with scope inclusion [HRF]. The happens-before relation is transitive over the synchronizes-with relation independent of scope and synchronizes-with allows the memory scope instances to be inclusive (see table AMDHSA LLVM Sync Scopes). This is different to the OpenCL [OpenCL] memory model which does not have scope inclusion and requires the memory scopes to exactly match. However, this is conservatively correct for OpenCL. The AMDGPU backend implements the following LLVM IR intrinsics.

The memory model supported is based on the HSA memory model [HSA] which is based in turn on HRF-indirect with scope inclusion [HRF]. The happens-before relation is transitive over the synchronizes-with relation independent of scope and synchronizes-with allows the memory scope instances to be inclusive (see table AMDHSA LLVM Sync Scopes). This is different to the OpenCL [OpenCL] memory model which does not have scope inclusion and requires the memory scopes to exactly match. However, this is conservatively correct for OpenCL. The AMDGPU backend implements the following LLVM IR intrinsics.

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October 19, 2021 - The memory model supported is based on the HSA memory model [HSA] which is based in turn on HRF-indirect with scope inclusion [HRF]. The happens-before relation is transitive over the synchronizes-with relation independent of scope and synchronizes-with allows the memory scope instances to be inclusive (see table AMDHSA LLVM Sync Scopes). This is different to the OpenCL [OpenCL] memory model which does not have scope inclusion and requires the memory scopes to exactly match. However, this is conservatively correct for OpenCL. The AMDGPU backend implements the following LLVM IR intrinsics.