Computing will get more heterogenous and stratified, with different kinds of computing devices more strongly optimized for different roles. Handheld devices and laptops will converge into a class of lightweight devices which will subsume all desktop/workstation roles in addition to the functions of smartphones and tablets. They will be phablet-sized with the option of using a docking station for use with a full-sized display and keyboard, and a more comprehensive array of I/O ports. Processors for these devices will consolidate the current E-core/P-core/GPU dichotomy into a small number of P-cores designed for very high single-threaded performance and a large number of shader-like (but more general-purpose) efficiency cores with lower clock rates, smaller caches, and high aggregate capacity. When not used with a docking station, the P-cores will turn entirely off, so that only the energy-efficient E-core/shader cores are drawing battery power. Die-stacked HBM memory will become more prevalent, and more dense, so that the entire main memory will sit on-die with a large number of wide memory channels, eliminating current memory bottlenecks. Eventually the problem of mixing logic and DRAM on-die will be solved, allowing three advances: The tighter integration of stacked memory, the use of on-die DRAM as processor cache, and greater use of Processor-in-Memory technology, as seen in recent Samsung offerings -- https://www.digitimes.com/news/a20230831PD204/memory-chips-samsung-semiconductor-research.html Right now Samsung's PIM implementation suffers from large, slow logic, necessitated by the contradictory requirements of DRAM and logic, but they've been hitting a happy compromise with net benefits despite that. I expect this technology to continue to improve. That's for the consumer-side of things. For the datacenter, wafer-scale processors (as championed by Cerebras) make a lot of sense, IMO. If a cloud provider needs a hundred thousand servers, why cut up a thousand wafers into a hundred processors each, only so you can reconnect them as best you can with large, clunky, slow, narrow interconnects? Keep them interconnected on the wafer instead, and just use a thousand wafer-scale processors instead of a hundred thousand conventional ones. Right now the main drawbacks of wafer-scale processors are limited main memories (since we haven't licked the logic/DRAM puzzle yet, they have to use SRAM for main memory, which is intrinsically low-density) and heat dissipation. The main memory problem will be addressed first with wafer-scale stacked HBM DRAM (which unfortunately exacerbates the heat dissipation problem) and eventually with the same unified logic/DRAM solution postulated above for consumer devices. For the heat dissipation problem, I'm not sure what to suggest. Smaller voltage swings and lower clock rates, for sure, but beyond that I defer to better minds more intimately familiar with the technology. More on reddit.com

It is ridiculous. ChatGPT takes seconds to write a 500-word essay on any topic you ask.

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