The CPU has a dedicated area of memory called the interrupt (vector) table. There's one entry per interrupt type, and each entry points to a memory address. When an interrupt happens, the CPU immediately stops, looks up the address in the table, and jumps to it. From there, it's up to the interrupt handler to run, which is obviously software defined. OS interrupts, not hardware interrupts, can be done by loading a value into a CPU register as your interrupt type, then triggering a dedicated hardware interrupt, where the handler jumps again to the appropriate point in the OS vector table, handing control back to the OS to perform it's actions. Once the handler has finished running, it signals a return which causes previous execution to continue. Raw hardware interrupts are not a multithreaded ordeal themselves, but since actual behavior is completely software based, should the handler wish to use parallel capabilities, it can do so. OS interrupts are a little different in those regards, but usually function close to the same way, however you can have a case where only a single core is interrupted by the OS, for example, to signal that a disk transfer has completed. Edit 1: am not a cpu engineer, this is all stated to the best of my knowledge. Edit 2: drinking game: take a swig every time you read "interrupt" More on reddit.com

It depends on the operating system / microcontroller that you are talking about, but generally speaking they are queued and executed in order, and they can cause problems if they arrive faster than they can be serviced over a long period of time. See Interrupt Storm . More on reddit.com

The CPU just executes your program instructions endlessly.. so it needs to be told to do something different. There is likely a interrupt controller that handles this communication with the CPU and also deals with configuration of interrupt vectors (such as turning on/off vectors, priority masking, multi-vector, etc.) for the programmer In it's most basic form, the CPU only has to receive a digital pulse that it needs to jump to an interrupt vector, and if the CPU supports multiple vectors, which vector that is. Then the CPU needs to know which program location it needs to jump to in order to serve that interrupt. There is no specific standard for this, as each architecture does this different, but a simple example would be an interrupt vector table. This is basically an array of addresses which is indexed by the IRQ vector number. The MCU vendor hardcodes (or hardwires more specifically) certain IRQ vector numbers to certain interrupts. The address is basically the location at which the IRQ vector function is stored at. Now there are far more specifics in how to actually enter/exit interrupts. Some MCUs require explicit return instructions from interrupts, as their CPU is doing extra tricks under the hood. E.g. MIPS and older ARM CPUs had something called a shadow register set: these are present to reduce interrupt latency. As an interrupt can happen anywhere in the program and looks a lot like an unpredictable function call, the function that is being called (the IRQ vector) needs to store registers from the main program temporarely. Upon exit it also needs to restore them. This costs instructions and time. A shadow register set basically does this in hardware within 1 cycle, but requires some parts of the register file to be duplicated. Not all modern MCUs have this anymore, because IRQ latency used to be quite atrocious and is fairly reasonable now. Also, modern MCUs are better equipped with peripherals that don't always need high interrupt rates or CPU intervention, so it's less big of a deal. If you want ultimate timing predictability though, you wouldn't use a CPU to begin with. But there is a lot more to it than this. I highly recommended reading Patterson and Hennessy's book. It's a great into in how computers (and therewith MCUs) work. Also there are vendor documentations for IRQ controllers and whatnot, but those usually have quite a high jargon density that's a bit dry to go through. But it could be worth a try. edit: thanks for gold! More on reddit.com

Yes, because Turing completeness. Yes, just use longjmp. That's the way it was done historically. Yes, check out the wild shenanigans that Chicken Scheme manages to compile down into C! Yes: The C++ community is currently having a discussion about alternatives to exceptions that come with less runtime overhead. See: Zero-overhead deterministic exceptions: Throwing values status_code and standard error object for Zero-overhead deterministic exceptions C++ exceptions and alternatives P0323R10: std::expected More on reddit.com