That's a ternary operator. It's shorthand for an if statement

Format:

condition ? if true : if false

Example:

tone[23] ? clkdivider-1 : clkdivider/2-1

Translates to something like (not correct syntax but I think you'll get it):

if tone[23] is 1, counter = clkdivider-1
else counter = clkdivider/2-1

Here are two examples of a 2 to 1 MUX using if statement and ternary operator.

On the asic-world website, it is covered under Conditional Operators

There's no need for the ternary operator here. The result of each equality(==) is 1-bit, and you are doing a bit-wise OR (|). You probably should be using a logical OR (||) whose result is also 1-bit.

assign F = (BCD == 4'd1 || BCD == 4'd2 || BCD == 4'd3 || BCD == 4'd4 || BCD == 4'd5);

In SystemVerilog which most tools are supporting, you can use the inside operator

assign F = BCD inside {[1:5]}; //  contiguous range
assign F = BCD inside {[1:3],5, [7:10]}; //  noncontiguous values

Formatting

There is nothing wrong with a nested conditional continuous assignment, but there are ways to make it more readable:

assign a = (b)    ? '1
         : (c&d)  ? '0
         : (f&h)  ? '1
                  : '0;

However, this is still an "if...else if...else if...else" structure, and a question you should ask yourself is what is this code meant to do and how it would 'read'. The above may be easier to read (while synthesizing same code) if it is code using an always and ""if...else if...else if...else" structure.

Here is an example of a clean use of the nested conditional continuous assignment:

assign a = (state == STATE1) ? '1
         : (state == STATE2) ? '0
         : (state == STATE3) ? '1 
           /* default */     : '0;

Readability

Do consider, that your shown form may save time in the original typing of the code, but there is much higher value in having your code readable. Be it yourself, or another designer, looking at the code a year or more later will appreciate a form that allows them to quickly grasp what the logic is doing.

Coding can be sped up without loss of readability by using an editor that supports auto-expanding snippets (or abbreviations). I use vim with abbreviations that really speed up all block structure entry, and alignment scripts that allow me to vertically align given character (like "=" or "(") or string in selection.

If you want to use the ternary (conditional) operator, you can use case equality (===) instead of logical equality (==):

i0_reg <= (i0_reg === 0 ? (1'bz) : 0);

Refer to IEEE Std 1800-2017, section 11.4.5 Equality operators.

The behavior you observed is not a bug and it is not specific to iverilog; it is observed on other simulators as well.

In your original ternary code, when i0_reg has the value 1'bz, then the expression i0_reg == 0 evaluates to 1'bx, and i0_reg is assigned the value 1'bx.