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element14 Community
community.element14.com โ€บ challenges-projects โ€บ project14 โ€บ backtoanalog โ€บ b โ€บ blog โ€บ posts โ€บ pseudo-random-number-generator
Pseudo random number generator - element14 Community
Below there is logic circuit of this PRNG: We have here 3 bit shift register which input is feed from XOR gate which is connected to two outputs from this register. It allows to generate number from range 1-7 in according to clock signal. To get here better random sequence you could use generator based on avalanche noise.
algorithm that generates a sequence of numbers whose properties approximate those of sequences of true random numbers
A pseudorandom number generator (PRNG), also known as a deterministic random bit generator (DRBG), is an algorithm for generating a sequence of numbers whose properties approximate the properties of sequences of random โ€ฆ Wikipedia
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Wikipedia
en.wikipedia.org โ€บ wiki โ€บ Pseudorandom_number_generator
Pseudorandom number generator - Wikipedia
February 7, 2026 - They are generally used for generating pseudorandom numbers for large parallel computations, such as over GPU or CPU clusters. They have certain advantages: The only "state" needed is the counter value and the key. For a given counter and key, the output is always the same. This property makes CBRNGs reproducible. Because each random number is computed independently of any previous outputs, they can be generated in parallel.
Discussions

Simple Pseudo Random Number Generator with complete sequence
It is a circuit that can produce a pseudo-random sequence with a period of 2^n numbers, where n is the numbers of registers. The general and low resource approach to produce a pseudo-random sequence in hardware is to use Fibonacci or Galois linear-feedback shift register (LFSR) but the period of the generated ... More on forum.allaboutcircuits.com
๐ŸŒ forum.allaboutcircuits.com
7
January 7, 2020
Combinator Pseudo Random Number Generator
For another project I was working on I needed a free-running random number generator. Maybe others might find it useful. Image !blueprint: https://pastebin.com/sTsVp7iU The main PRNG is marked by green in the above image, with the output block in white. The output block comes configured to output positive values, but can be changed (to X+0) to output negatives too. (The output block could actually be removed in that case. Make sure to use a green wire to connect if you do that.) The PRNG needs to be seeded with some initial values and that is what the block in red accomplishes it. Change the A,B,C,D,E and F values in the constant combinator to something random. Then turn the constant combinator to On to start the PRNG running. The seeder block can be deleted after this. As an alternative to using new seed values every time, you can also use a source of entropy to cause the random sequence to diverge over time. The block marked in orange serves this purpose. Connect some intermittently varying signal (a good example would be a rail signal) to the block and configure the comparison operation appropriately. Do not change the output settings. This block is purely optional, remove it if you don't need the functionality. --- The above is (loosely) based on the Xorshift class of PRNG. I used the simplest variant because I didn't see any need to be paranoid about the quality of the random numbers. (One thing to note, this RNG cannot generate a value of exactly 0, if that is important to you.) If you want to play around with it, here is my development version: Image !blueprint: https://pastebin.com/yUhrXjDQ On the right is the version based on the original algorithm. The plus blocks are (X+0), and serve as delay blocks the so the xor uses the same input value as the preceding shift. This is needed because inputs and outputs of combinators are processed once per update. Without the delay, we would not be xoring the original value with it's shifted value, as the algorithm requires. As a consequence of the timing, we are actually running 6 PRNGs in parallel, pipelined (it takes six updates for the input to cycle through all blocks and loop back around). This is why the seeder needs 6 seed values and a timer to feed them in sequence. That said, I optimized the process by removing those delays. Even though this violates the original algorithm, I don't believe it should affect the result significantly. Basically, the 6 parallel RNGs are now being mixed together rather than being entirely separate. As they mix together their results should maintain their desirable random properties. My (limited) tests bear this out. For testing, I took the two most common cases I expect this will be used. Bernoulli random variables can be most easily generated with just a comparison against a constant. I tested this and checked that the mean matched the expected value. The other common case I see is needing discrete uniform values, most easily implemented using a modulus operation (with possibly an offset via constant combinator). I tested this as well, counting the output values and verifying the distribution appeared uniform. The point where the entropy injector connects was also selected based on the above. Bernoulli random variables generated in that way use the high-order bits, while the above discrete uniform uses low-order bits. As such, I elected to insert into the middle-order bits so that it would take some time to mix into the more important parts of the output. Side note: If anyone is wondering about the pattern of concrete and hazard concrete, I use this when designing dynamic circuits, where the timing is important. Each strip of hazard concrete marks an update. Except for loops, connections only move sideways or upwards. Loops are marked by power poles so they are always obvious (except for well known single block loopbacks like counters, SR latches, etc). Organizing this way helps me keep straight when exactly operations happen so that I can keep outputs synchronized where needed. --- Edit 2020/12/22: It appears pastebin has deleted the original links, so I will post the full blueprint string below for posterity. XORShift PseudoRNG: 0eNrtmltvmzAUx7+LX0cnfAMSbZN63ds29anVNEU0cTdLCUTGVKuqfPfZIUtIwsWHkcvDXloF7GN8fudvDsd+Q0/TXMyVTDQaviE5TpMMDb+/oUz+TOKpvaZf5wIN0YtUOjdXPJTEM3uhaHHxDS08JJOJ+I2GeOEBet6XehJQzy+lnhTU83OpJ1v88JBItNRSFJNe/ngdJfnsSSgznXXvWEn9aya0HF+M09mTTGKdKmN8nmamd5rYkY3FC+KhV/OPvedmGONLrdLp6En8il+kaW8abQyNzO3JsnNmbzxLlemR8zwe7DwyYW1YQ5mOLUCCWcgiGrDQQ+lcqLh4NnT55cZYSHM9z2FjLIppJGK8flBs//xUQiRll8mJGd20lWqcS138XPyw/fe8SsBepe954VfDGk2kKp6mGPBIPnbu9Gg7lX3/8PW+X98rMdn1PN32PLaBXYmI7iPyEKmxyl2t4r2GleBpd/BkG3xwCnFhvg32w4cOXB9BXMmuY72t26yWpos+6zAxMCZ8ekznrc/AVUkBRJ/UjSfvzvN0621JdvTUsiM7sgubVYkxTJahG8YAitE/q8VzJyP59OngFFkzphBGqcVa5Jb7hJ0h/k99/jFJ4ZClNXDTZLR+9okYy4lQjSyB2czK5A7IjaR82202j9VyNLMwdlOUtTJ/NaPkiR49q3Q2komxgYbP8TQTFSTqNRK4iWAAfiGxpd/8g39VXVauXf52VL87eExjfz/86mN1t3Wd2207aP59JL9fnYffB7AXezOWQXMSUZUlVFLrWoQ4PLXrc1XLjqfJv6nJa37fNA9WixVeBcFHwnpzJlhxi6dpy/0I8sLfl2PzaLVcwUUO/0hYb88Ea0tNAzOQWls+1TBzxAYuehxLjXdngo2CsLiqhYMS6FUeSGqdXp0yAz3uFznx+st1J83+2MHXlw1ptla5AJXZcQBC4ZiU4wCGgp4ABekBxVWvKNqygRCEircsZqEjyhCGkpwAJe0B5fVhVdWcTkBV156cVKKEVRhWOeJxUbIeUN70irKtQNvynUcIKHMMW1AT2NPUhsIAFAr+CSKB9xAJt71GQtRCGlZoiZpJE8dCDPFBJE+h6aAHkne9khyASDlqimyKK3/n7pL1sBoSz3KqhQKen1nlhrl1+wVn3A8p57zjkZqrLWM0ijDDdjnrdMrmumQsYngwICzqeOzmpmQqCCgPOQui0kEciK3b8hwjGuBoENrvt5UxDjJ2VzIWBpwx82Ab5wcgW0XgbuzhDcQQZMivNhLZvQ2ZjWw4FsV5yOEcx91/QoAZx2pTgzntT/WyVpX8XLcX0mV30e9zvSIthQmC2w5rEHg+ulgGiBYzM6nNsT4PvZhFqdhpikKCjWR8yhaLP74Tps0= (Unfortunately, the development version is too long to post here.) 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46
January 29, 2018
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Harvard SEAS
people.seas.harvard.edu โ€บ ~salil โ€บ pseudorandomness โ€บ prgs.pdf pdf
7 Pseudorandom Generators 7.1 Motivation and De๏ฌnition
H(x), then G is an (m,1/m) pseudorandom generator. ... De๏ฌnition 7.26. An unbounded fan-in circuit C(x1,...,xn) has input ยท gates consisting of variables xi, their negations ยฌxi, and the constants ยท 0 and 1, as well as computation gates, which can compute the AND ยท or OR of an unbounded number of other gates (rather than just 2, as
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Developer Help
developerhelp.microchip.com โ€บ xwiki โ€บ bin โ€บ view โ€บ products โ€บ mcu-mpu โ€บ 8-bit-mcu-tips-tricks โ€บ configurable-logic-block โ€บ prng
How to Create a Pseudo-Random Number Generator (PRNG) - Developer Help
January 9, 2026 - This example demonstrates a PRNG using the Configurable Logic Block (CLB) and Serial Peripheral Interface (SPI) peripheral, with the SPI acting as a shift register and the CLB generating the Linear Feedback Shift Register (LFSR) tap feedback and control signals. This hardware-based approach enables continuous, efficient pseudo-random number generation without burdening the CPU.
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Google Patents
patents.google.com โ€บ patent โ€บ US4905176A โ€บ en
US4905176A - Random number generator circuit - Google Patents
A variation of the free-running ring oscillator is employed as the pseudo-random number generator, by introducing into the feedback loop of the ring oscillator, an exclusive OR circuit which is connected so that the ring oscillator thereby produces a serial, pseudo-random number sequence.
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All About Circuits
forum.allaboutcircuits.com โ€บ home โ€บ forums โ€บ hardware design โ€บ general electronics chat
Simple Pseudo Random Number Generator with complete sequence | All About Circuits
January 7, 2020 - It is a circuit that can produce a pseudo-random sequence with a period of 2^n numbers, where n is the numbers of registers. The general and low resource approach to produce a pseudo-random sequence in hardware is to use Fibonacci or Galois ...
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GlobalSpec
globalspec.com โ€บ reference โ€บ 75841 โ€บ 203279 โ€บ 14-7-pseudo-random-sequence-generators
14.7: Pseudo-Random Sequence Generators | GlobalSpec
Pseudo-random sequences are normally generated using a circuit called linear-feedback shift register (LFSR). As illustrated in Figure 14.30(a), it consists simply of a tapped circular shift register with the taps feeding a modulo-2 adder (XOR gate) whose output is fed back to the first flip-flop.
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CircuitVerse
circuitverse.org โ€บ users โ€บ 144874 โ€บ projects โ€บ pseudo-random-number-generator
CircuitVerse - Pseudo Random Number Generator
September 18, 2022 - A 5-bit pseudo random number generator. Uses 5 D Flip-Flops to form a linear feedback shift register. The generator stops when put in a lock state of 00000. Push the button to start.
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MDPI
mdpi.com โ€บ 2072-666X โ€บ 12 โ€บ 1 โ€บ 31
A Hardware Pseudo-Random Number Generator Using Stochastic Computing and Logistic Map
December 30, 2020 - In [12], an algorithm for generating multiple pseudo-random sequences using chaotic functions was developed. The initial values of the chaotic system are calculated and indexed by a based-chaos linear congruences function. All of the above methods are chaos-based PRNGs, and are all realized using software. In addition, many researchers have contributions in hardware implementation of chaos-based PRNGs. In [13], fully digital circuits are used to implement a chaos-based PRNG, and the clock frequency achieves 120 Mhz.
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Quora
quora.com โ€บ How-do-I-build-a-3-bit-pseudo-random-number-generator-circuit-using-logic-ICs
How to build a 3 bit pseudo-random number generator circuit using logic ICs - Quora
Answer: You need a linear feedback shift register. Three bits is too few for robust randomness, the output sequence will repeat after it cycles through seven permutations. Depending on your requirements, a better result would be obtained using ...
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ResearchGate
researchgate.net โ€บ figure โ€บ Pseudo-Random-Number-Generator-Circuit-512-bits_fig5_366312917
Pseudo-Random Number Generator Circuit (512 bits) | Download Scientific Diagram
... we are generating a pseudo-random number of lengths 512. The primitive polynomial used for it is p 9 +p 4 + 1. Fig. 5 shows the detailed circuit diagram to generate 512 bits PRNG. Here we have used 9 no.
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IEEE Xplore
ieeexplore.ieee.org โ€บ document โ€บ 10557718
Pseudo-Random Number Generators for Stochastic Computing (SC): Design and Analysis | IEEE Journals & Magazine | IEEE Xplore
In most nanoscale stochastic computing designs, the Stochastic Number Generator (SNG) circuit is complex and occupies a significant area because each copy of a stochastic variable requires its own dedicated (and independent) stochastic number generator. This article introduces a novel approach for pseudo-random number generators (RNGs) to be used in SNGs.
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Circuit Cellar
circuitcellar.com โ€บ home โ€บ a hardware random number generator
A Hardware Random Number Generator - Circuit Cellar
January 29, 2021 - FIGURE 2 โ€“ Circuitry for the linear-feedback shift register random number generator. The shift register outputs hexadecimal digits, but the 4511-display driver only shows 0-9 and blanks hex digits A-F. The authorโ€™s original TTL circuit used a 7447-display driver that outputs arbitrary characters for inputs beyond 9.
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GitHub
github.com โ€บ amri-tah โ€บ Pseudo-Random-Number-Generator-LFSR-Algorithm
GitHub - amri-tah/Pseudo-Random-Number-Generator-LFSR-Algorithm: Pseudo Random Number Generator using Linear Feedback Shift Register created as a part of the course "Elements of Computing Systems-01" ยท GitHub
In simple terms, the feedback polynomial is like a set of rules that tell the LFSR how to generate its output sequence. The coefficients of the polynomial represent the taps (or positions) in the shift register that contribute to the next value in the sequence. For example, an 8-bit LFSR, the feedback polynomial is๐‘ฅ8+๐‘ฅ6+๐‘ฅ5+๐‘ฅ4+1=0. Hence, outputs of flipflops 8,6,5,4 are summed via XNOR gates and fed back into the first flip-flop. The seed in a Pseudo Random Number Generator (PRNG) implemented using a Linear Feedback Shift Register (LFSR) is the initial state of the LFSR.
Author ย  amri-tah
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Hackaday
hackaday.com โ€บ 2019 โ€บ 04 โ€บ 23 โ€บ the-simplest-of-pseudo-random-number-generators
The Simplest Of Pseudo Random Number Generators | Hackaday
April 23, 2019 - By contrast it is extremely easy to generate numbers that look random but in fact follow a predictable sequence. A shift register with feedback through an XOR of its output and one of its stages will produce a continuous stream of pseudo-random bits that repeat after a set period.
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IEEE Xplore
ieeexplore.ieee.org โ€บ document โ€บ 10231187
A Pseudo-Random Number Generator Circuit for Nanoscale Stochastic Computing (SC) | IEEE Conference Publication | IEEE Xplore
In most nanoscale stochastic computing designs, the Stochastic Number Generator (SNG) circuit is of primary importance, but it may require considerable area due to its complexity. This paper proposes a new design for pseudo-random number generators (RNGs) to be used in SNGs.
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Electro Tech Online
electro-tech-online.com โ€บ electronics forums โ€บ electronic projects design/ideas/reviews
Pseudo-Random number generator with a complete numerical sequence | Electronics Forum (Circuits, Projects and Microcontrollers)
April 22, 2020 - It is a circuit that can produce a pseudo-random sequence with a period of 2^n numbers, where n is the numbers of registers. The classical approach to generate pseudo-random numbers is to use Fibonacci or Galois linear-feedback shift register ...
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Wikipedia
en.wikipedia.org โ€บ wiki โ€บ Pseudorandom_generator
Pseudorandom generator - Wikipedia
October 16, 2025 - In theoretical computer science and cryptography, a pseudorandom generator (PRG) for a class of statistical tests is a deterministic procedure that maps a random seed to a longer pseudorandom string such that no statistical test in the class can distinguish between the output of the generator and the uniform distribution. The random seed itself is typically a short binary string drawn from the uniform distribution. Many different classes of statistical tests have been considered in the literature, among them the class of all Boolean circuits of a given size.
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Make:
makezine.com โ€บ home โ€บ really, really random number generator
Really, Really Random Number Generator - Make:
March 15, 2023 - This is why almost every computer game uses a random-number generator in its program code, to add an element of surprise. In my book Make: More Electronics I showed how to satisfy this need in hardware, using a linear feedback shift register. It creates a pseudo-random stream of low and high states as a logic output โ€” but the stream repeats after only 255 cycles, which is a significant limitation.