See this article

Uncertain Circuits: When transistor 1 and transistor 2 are switched on, a coupled pair of inverters force Node A and Node B into the same state [left]. When the clock pulse rises [yellow, right], these transistors are turned off. Initially the output of both inverters falls into an indeterminate state, but random thermal noise within the inverters soon jostles one node into the logical 1 state and the other goes to logical 0.

Also see the white paper (Respawned Fluff note: This is for an older Intel method, using two free-running oscillators, not the one described above.)

Answer from Math1000 on Stack Exchange
🌐
IEEE Xplore
ieeexplore.ieee.org › abstract › document › 5724498
A digital IC Random Number Generator with logic gates only | IEEE Conference Publication | IEEE Xplore
Random Number Generators with logic gates only are popular among digital IC designers in terms of their speed compatibility and uncomplicated integration to digital platforms. To the best of our knowledge, this paper presents the first ASIC ...
🌐
Springer
link.springer.com › home › cryptographic hardware and embedded systems - ches 2007 › conference paper
High-Speed True Random Number Generation with Logic Gates Only | SpringerLink
The restart and continuous modes of operation and a novel sampling method almost doubling the entropy rate are proposed. Accordingly, the new oscillators appear to be by far more effective than other known solutions for random number generation with logic gates only.
🌐
International Association for Cryptologic Research
iacr.org › workshops › ches › ches2007 › presentations › S2T1-Dichtl.pdf pdf
1 High-Speed True Random Number Generation with Logic Gates Only Markus Dichtl
High-Speed True Random Number · Generation with Logic Gates Only · Markus Dichtl · Jovan Golić · 2 · Being One Year Late · You should have heard this talk at · CHES 2006, but … · 3 · Why We Need Random Numbers from · Logic Gates · Many cryptographic protocols need random numbers ·
🌐
Google Patents
patents.google.com › patent › US20070273408A1 › en
US20070273408A1 - Random Number Generation Based on Logic Circuits with Feedback - Google Patents
An output sequence OSa of the first oscillator 400 a and an output sequence OSb of the second oscillator 400 b are combined together, for example, they are bitwise XOR-ed by a two-input XOR gate 405 . the resulting output sequence OS is fed to the sampling unit 125 , operated by a clock signal Ck, producing the raw binary sequence RBS. the structure of FIG. 4 further enhances the randomness properties and increases their robustness with respect to changes in the statistics of the random variations in the delay of the logic inversion units.
🌐
ResearchGate
researchgate.net › publication › 226148194_High-Speed_True_Random_Number_Generation_with_Logic_Gates_Only
(PDF) High-Speed True Random Number Generation with Logic Gates Only
November 21, 2024 - The first is a true random number generator (TRNG) which employs oscillator phase noise, and the second is a bit serial implementation of a Blum Blum Shub (BBS) pseudorandom number generator (PRNG).
Find elsewhere
🌐
Nature
nature.com › scientific reports › articles › article
Scalable true random number generator using adiabatic superconductor logic | Scientific Reports
November 21, 2022 - In the present study, we propose a scalable true-random-number generating scheme that we refer to as XORing shift registers (XSR) and implement XSR using AQFP logic. XSR generates multiple uncorrelated true random bitstreams in parallel using only two TRNGs as entropy sources. This is a huge advantage in the development of large-scale systems. In general, a TRNG is a somewhat complex circuit (various TRNGs can be found in the literature28,29,30,31,32,33), and minimizing their number is highly desirable. Since XSR utilizes XOR gates to generate multiple random bitstreams, we first explain random number generation using XOR gates.
🌐
element14 Community
community.element14.com › challenges-projects › project14 › backtoanalog › b › blog › posts › pseudo-random-number-generator
Pseudo random number generator - element14 Community
The basic idea was to create simple circuit with usage transistors, 4000 and 74HC series integrated circuits. I have created 3 bit random number generator with graphical presentation.
🌐
Quora
quora.com › How-do-I-build-a-3-bit-pseudo-random-number-generator-circuit-using-logic-ICs
How to build a 3 bit pseudo-random number generator circuit using logic ICs - Quora
Answer: You need a linear feedback shift register. Three bits is too few for robust randomness, the output sequence will repeat after it cycles through seven permutations. Depending on your requirements, a better result would be obtained using ...
🌐
Standoutpublishing
standoutpublishing.com › Blog › archives › 78-True-Random-Number-Generator-Using-Only-Logic-Gates.html
True Random Number Generator Using Only Logic Gates? - Loligo Blog
“You should call it entropy, because nobody knows what entropy really is, so in a debate you will always have the advantage.” — John Von Neuman, to Claud Shannon (strikes me that you could apply the same advice to the term "computer science," just sayin' ) · Exploring new approaches ...
🌐
Google Patents
patents.google.com › patent › US20030061250A1 › en
US20030061250A1 - Random number generating circuit - Google Patents
The random number generating circuit includes an uncertain logic circuit having a flip-flop type logic circuit that gives digital output values not determined definitely by a digital input value, and an equalizing circuit having an exclusive OR operating circuit for equalizing appearance ...
🌐
International Association for Cryptologic Research
iacr.org › archive › ches2007 › 47270045 › 47270045.pdf pdf
High-Speed True Random Number Generation with Logic ...
The proceedings of some conferences past are made available by the IACR. The copyright for all papers after 2000 is held by the IACR
🌐
Circuit Cellar
circuitcellar.com › home › a hardware random number generator
A Hardware Random Number Generator - Circuit Cellar
January 29, 2021 - In a Fibonacci linear-feedback ... of bits from the stages of the shift register. Exclusive-Or (XOR) logic gates combine bits in a way that maximizes the randomness....
🌐
Fandom
creativerse.fandom.com › wiki › Random_Number_Generator
Random Number Generator | Creativerse Wiki | Fandom
January 9, 2026 - The Random Number Generator is a logic gate that can be wired in between activation devices (for example Number Pads, Industrial Number Pads, Sensors, Switches or Pressure Plates) or other logic gates (including Inverter Gates, Flip-Flop Gates, ...
🌐
Semantic Scholar
semanticscholar.org › papers › high-speed true random number generation with logic gates only
[PDF] High-Speed True Random Number Generation with Logic Gates Only | Semantic Scholar
A new method for digital true random number generation based on asynchronous logic circuits with feedback based on the so-called Galois and Fibonacci ring oscillators is introduced and a concrete technique using a self-clock-controlled linear ...
🌐
IEEE Xplore
ieeexplore.ieee.org › document › 9086084
Hardware Random Number Generator Using Josephson Oscillation and SFQ Logic Circuits | IEEE Journals & Magazine | IEEE Xplore
The logic circuit of the random number generator consists of one toggle flip flop and one and gate. A prototype random number generator is designed by logic cells based on a 2.5-kA/cm2 Nb/AlOx/Nb integration process.
🌐
Semantic Scholar
semanticscholar.org › papers › a digital ic random number generator with logic gates only
A digital IC Random Number Generator with logic gates only | Semantic Scholar
This paper presents the first ASIC implementation of a Random Number Generator based on Fibonacci and Galois ring oscillators, and proposes to use several of these oscillators in an xored configuration, in order to speed up and improve the quality of the generated bit stream.Expand
🌐
arXiv
arxiv.org › abs › 1209.0142
[1209.0142] Ultra-Fast Physical Generation of Random Numbers Using Hybrid Boolean Networks
April 17, 2013 - Abstract:We describe a high-speed physical random number generator based on a hybrid Boolean network with autonomous and clocked logic gates, realized on a reconfigurable chip. The autonomous logic gates are arranged in a bidirectional ring ...