I will attempt to answer this fairly vague question by listing the high level steps to set up a timer interrupt, to help point you in the right direction.

• Turn on the timer peripheral by enabling it's clock. This is done via the RCC subsystem. You will find this kind of register manipulation in any STM32 code example. If you are going to use the timer for e.g. PWM waveform generation, or to measure external signals, you will also need to enable the clock for the GPIO port you are using. I assume you are past the general "blinking LED" stage and will not go into more detail about GPIO ports :)
• Configure the timer peripheral to generate interrupts in response to specific timer events. This is not covered in the NVIC section of the manual, but in the section about timers. For the STM32F103 and probably other STM32 chips, the register is called DIER. You will likely want to set the UIE bit in this register, however don't take my word for it. You should read the whole section of the manual to understand how the timer works and how to set it up.
• Enable the correct IRQ in the NVIC. This hardware (the NVIC) is not specific to STM32, but is common to all ARM microcontrollers. Each interrupt line on the chip (there may be one dedicated to the timer you are using, or it might be shared by several peripherals) is referred to by an integer. I usually look in the device header file for this information, and I recommend getting comfortable with looking through the vendor code for answers about the chip you're working with.
• Implement your interrupt handler function, often referred to as an ISR (Interrupt Service Routine). In C code, you declare a function which is already named elsewhere in the vendor's initialization code. When you declare a function with that name, the compiler/linker will know to place the address of that function into a known location (the vector table, another good thing to look up). This is the part of the code where you will toggle your LED. It is important to note that each peripheral that can generate an interrupt has a status bit that your ISR should clear, to acknowledge that the ISR has been executed. This becomes important when you have an IRQ shared by multiple peripherals, or if you want to handle more than one event generated by one peripheral. For example, if you enable the "timer update" interrupt via the UIE bit, you will need to then clear the corresponding UIF bit in the status register. This is the only way the peripheral knows that the interrupt has been handled. If you don't do this, the chip will lock up because it is continuously entering the interrupt handler.

Other general advice: the book "The Definitive Guide To ARM Cortex-M3 and Cortex-M4 Processors" helped me understand a lot of this stuff, but not as much as closely reading the chip manual and vendor-provided code.

I am not going to take you entirely literally when you mandate "no libraries", because no one who wants to get work done and knows what they are doing on Cortex-M would do that - and I will assume at least that you will use the CMSIS - a common API provided for all ARM Cortex-M devices, and which makes your code more, not less portable.

All the CMSIS code is provided as source, rather than static library, so there is nothing hidden and if you chose not to use it, you can see how it works and replicate that functionality (needlessly) if you wish.

In the CMSIS default implementations are provided as "weak-links" that can be overridden by user code simply by defining a function of the pre-defined name to override the default. The default implementation is generally an infinite loop - so that unhandled interrupts are "trapped" so you can intervene with your debugger or wait for a watchdog reset for example.

The Cortex-M core interrupt handlers and exception handlers have common names across all Cortex-M parts:

Reset_Handler      
NMI_Handler        
HardFault_Handler  
MemManage_Handler  
BusFault_Handler   
UsageFault_Handler 
SVC_Handler        
DebugMon_Handler   
PendSV_Handler     
SysTick_Handler    

Peripheral interrupt handlers have names defined by the vendor, but the naming convention is <interrupt_source>_IRQHandler. For example on STM32F1xx EXTI0_IRQHandler is the shared external interrupt assigned to bit zero of GPIO ports.

To implement an CMSIS interrupt handler, all you need do is:

1. Implement the interrupt handler function using the CMSIS handler function name
2. Enable the interrupt in the NVIC (interrupt controller).

There other are things you might do such as assign the interrupt priority scheme (the split between preempt priorities and subpriorities), but lets keep it simple for the time being.

Because it is ubiquitous to all Cortex-M parts, and because it is useful in almost any non-trivial application an illustration using the SYSTICK interrupt is useful as a starting point.

#include "stm32f1xx.h"
  
volatile uint32_t msTicks = 0 ;
  
void SysTick_Handler(void)  
{
    msTicks++ ;
}
  
int main (void)  
{
    if( SysTick_Config( SystemCoreClock / 1000 ) != 0 ) // 1ms tick
    {
        // Error Handling 
    }
  
    ...

}

SysTick_Config() is another CMSIS function. In core_cm3.h it looks like this:

__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
  {
    return (1UL);                                                   /* Reload value impossible */
  }

  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
                   SysTick_CTRL_TICKINT_Msk   |
                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
  return (0UL);                                                     /* Function successful */
}

So let's say you have a external interrupt source on the falling edge of GPIOA pin 0, then you would use the STM32 EXTI0 interrupt. The minimal handler would look like:

void EXTI0_IRQHandler(void)
{
    EXTI->PR |= (1<<0);                           // clear pending interrupt

    // Handle interrupt...
}

Setting up the EXTI requires enabling the GPIO and the EXTI itself as well as the NVIC:

RCC->APB2ENR |= RCC_APB2ENR_IOPAEN ;           // enable clock for GPIOA
RCC->APB2ENR |= RCC_APB2ENR_AFIOEN ;           // enable clock for Alternate Function
AFIO->EXTICR[0] |= AFIO_EXTICR1_EXTI0 ;        // set pin to use

EXTI->IMR = EXTI_IMR_MR0 ;             // unmask interrupt
EXTI->EMR = EXTI_EMR_MR0 ;             // unmask event
EXTI->FTSR = EXTI_FTSR_TR0 ;           // set falling edge

NVIC->ISER[0] |= (1 << (EXTI0_IRQChannel & 0x1F));    // enable interrupt EXTI 0

The peripheral registers and structures are defined in stm32f10weakx.h, and the "weak" default peripheral handlers to be overridden are in startup_stm32f10x_cl.s for your specific part. Any handlers you override must match these symbol names exactly.

All the peripheral interrupt sources and how to configure them is defined un the ST Reference Manual RM0008.

All the Cortex-M core specific stuff - systtick, NVIC, exception handlers etc. is provided by ARM at https://developer.arm.com/ip-products/processors/cortex-m/cortex-m3

CMSIS for CM3 is documented at https://developer.arm.com/documentation/dui0552/a/

If timer supports the break functionality (and TIM1 does), then OC/OCN outputs are disabled after the reset. To enable them, set the MOE bit in the TIMx_BDTR register. In the libopencm3 this is done by timer_enable_break_main_output function.